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Digital Engineer I

Synaptics - Unit No. 402, 4th floor, Building No: 1 C, RMZ EcoSpace   Bengaluru   UNAVAILABLE

Posted 36 days ago

Salary: Not Disclosed

Tags: developer , engineer ,

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Overview

Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go.

 

We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics and video processing, combined with world class software and silicon development.

Responsibilities

Job Scope

Location: Bangalore

To drive the SOC verification in the Wifi 6 and wifi7 domain 

Provide technical leadership and expertise in the latest verification methodologies as well as Wifi domain.

To handle the verification of digital signal processing datapaths, Host Interfaces like PCIe, high speed interfaces, embedded microcontrollers 

As a Verification lead, work with the latest verification methodologies from block level, subsystem level and SOC level.

Drive innovations in the verification flow to improve performance, reusability. 

Job Responsibilities

Drive decision on methodologies to be adopted for verification

Drive the methodology for digital only, analog-digital verification environment, emulation platform as well as portability of block level TB/tests to SOC level

Architect the testbench and develop in UVM or Formal based verification approaches. 

Define testplan, tests and verification methodology for block / chiplevel verification. 

Work with design team in generating test-plans and closure of code and functional coverage.

Interaction with analog co-sim and Software team in enabling toplevel chip verification aspects and coming up with end to end scenarios.

Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team

Qualifications

Bachelor’s or Master’s degree in appropriate engineering discipline with 3+ years of experience in design verification.

Verification experience with UVM and constrained random, coverage-based verification approaches

Strong fundamentals in CPU architecture, Host interfaces like (PCIe, SDIO etc.), Bus interconnects specially AXI/ACE/AHB/APB.

Knowledge of assertion-based verification methods.

Proven track record as SOC DV lead of verifying logic designs/blocks/IP/SOC into high volume production

Excellent debugging and analytical skills

Should possess strong communication and leadership skills to ensure effective communication with Program Management or Engineering Management and group members

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